1. Field of the Invention
The present invention relates to field-effect transistor devices incorporated in, for example, amplifier circuits, oscillation circuits, and other electronic apparatuses.
2. Description of the Related Art
FIG. 8A is a schematic plan view showing an example of a field-effect transistor device (FET device) FIG. 8B is a schematic sectional view taken along the line Axe2x80x94A of the FET device of FIG. 8A as disclosed in Japanese Unexamined Patent Application Publication No. 63-164504. An FET device 30 of FIGS. 8A and 8B has a semiconductor substrate 31 made of GaAs, etc., and impurity ions, such as Si+, are implanted into the central portion of the semiconductor substrate 31, so as to form an active layer 32. A gate electrode 33 is formed on the surface of the active layer 32, and also, a source electrode 34 and a drain electrode 35 are formed so as to sandwich the gate electrode 33 with a space defined therebetween. The active layer 32, the gate electrode 33, the source electrode 34, and the drain electrode 35 define an FET portion.
On the surface of the semiconductor substrate 31, an electrode 36 used for a line to make a connection to the gate, connected to the gate electrode 33, is formed at the upper left portion of FIG. 8A. An electrode 37 used for a line to make a connection to the source, connected to the source electrode 34, is formed at the upper right portion of FIG. 8A. Furthermore, an electrode 38 used for a line to make a connection to the drain, connected to the drain electrode 35, is formed at the lower half portion of FIG. 8A.
The gate-connection-line electrode 36, the source-connection-line electrode 37, and the drain-connection-line electrode 38 define a signal line connected to the FET portion. That is, the drain-connection-line electrode 38 is grounded. The drain-connection-line electrode 38 has a portion 38a opposing the gate-connection-line electrode 36 with a space defined therebetween, and a portion 38b opposing the source-connection-line electrode 37 with a space defined therebetween. An electrode pair 40 of electrode portion 3Ba and gate-connection-line electrode 36, and an electrode pair 41 of electrode portion 38b and source-connection-line electrode 37 each functions as a slot line. The electrode pair 40 defines a FET input line, and the electrode pair 41 defines a FET output line.
In this FET device 30, for example, when a signal is input to the gate electrode 33 via the FET input line 40, the signal amplified by the active layer 32 is output externally through the FET output line 41.
In the configuration of the FET device 30, the gate electrode 33 has a configuration that extends along the conduction direction of the signal. For this reason, a phase difference occurs between the signal at the base-end portion of the gate electrode 33 and the signal at the front-end portion of the gate electrode 33, and when a high-frequency signal flows, the phase difference cannot be ignored. For example, when the phase difference between the signal at the base-end portion of the gate electrode 33 and the signal at the front-end portion thereof is approximately xcex/4 to xcex/2, the signal which is amplified on the basis of the signal at the base-end portion of the gate electrode 33, and the signal which is amplified on the basis of the signal at the front-end portion become 180xc2x0 out of phase with each other. As a result, portions of the signals amplified by the FET portion cancel each other, presenting a problem in that the gain (power amplification efficiency) of the FET portion is decreased.
In order to overcome the problems described above, preferred embodiments of the present invention provide a field-effect transistor device that is capable of increasing the gain without suffering the disadvantages and problems described above.
According to a preferred embodiment of the present invention, a field-effect transistor device includes a field-effect transistor portion including a gate electrode, a source electrode, and a drain electrode, the gate electrode being located on the surface of an active area located on a semiconductor substrate, and the source electrode and the drain electrode being arranged in such a manner so as to sandwich the gate electrode with a space provided therebetween; a gate-connection-line electrode defining a line for making a connection to the gate electrode; a source-connection-line electrode defining a line for making a connection to the source electrode, the gate-connection-line electrode and the source-connection-line electrode being arranged such that respective portions thereof oppose each other with a space provided therebetween; and an electrode used defining a line for making a connection to the drain electrode arranged in such a manner that a portion thereof opposes the gate-connection-line electrode with a space provided therebetween, the gate-connection-line electrode, the source-connection-line electrode, and the drain-connection-line electrode being disposed on the surface of the semiconductor substrate which is coplanar with respect to the surface on which the gate electrode, the source electrode, and the drain electrode are disposed, wherein one of the electrode pair portion where the gate-connection-line electrode opposes the source-connection-line electrode and the electrode pair portion where the gate-connection-line electrode opposes the drain-connection-line electrode functions as a slot line on the input side for inputting a signal to the field-effect transistor portion and the other of the electrode pair portion where the gate-connection-line electrode opposes the source-connection-line electrode and the electrode pair portion where the gate-connection-line electrode opposes the drain-connection-line electrode functions as a slot line on the output side from which a signal is output from the field-effect transistor portion, and wherein the gate electrode has a configuration which extends along a direction that is substantially perpendicular to the conduction direction of the signal flowing through the slot line on the input side or along a direction inclined with respect to the conduction direction of the signal flowing through the slot line on the input side.
The source-connection-line electrode and the drain-connection-line electrode may be arranged adjacent to each other with a space provided therebetween, and a cut-out portion may be formed in at least one of the electrode portion on the drain-connection-line electrode side in the source-connection-line electrode and the electrode portion on the source-connection-line electrode side in the drain-connection-line electrode. As a result, the space between the source-connection-line electrode and the drain-connection-line electrode is increased.
The slot line on the input side and the slot line on the output side may be arranged along approximately the same straight line and such that the field-effect transistor portion is disposed therebetween.
A plurality of sets of the gate electrode, the source electrode, and the drain electrode may be disposed on the same surface of the semiconductor substrate, the field-effect transistor device may include a plurality of field-effect transistor portions, and a slot line on the input side and a slot line on the output side, corresponding to each of the plurality of field-effect transistor portions, may be disposed on the semiconductor substrate.
An even number of field-effect transistor portions may be arranged with a space provided therebetween on the semiconductor substrate, and the entire electrode pattern of a plurality of sets of the gate electrode, the source electrode, and the drain electrode, the gate-connection-line electrode, the source-connection-line electrode, and the drain-connection-line electrode, which are disposed on the surface of the semiconductor substrate, may be arranged to have a pattern shape which is approximately line symmetrical with respect to the center line of that entire electrode pattern, which is substantially perpendicular to the direction in which the field-effect transistor portions are arranged.
According to various preferred embodiments of the present invention, since the gate electrode which is a constituent of the field-effect transistor portion preferably has a shape which extends along a direction normal to the conduction direction of the signal flowing through he slot line on the input side or along a direction inclined with respect to the conduction direction of the signal flowing through the slot line on the input side, it is possible to eliminate the phase difference of the signal within the gate electrode or possible to minimize the phase difference. As a result, it is possible to prevent a decrease in gain resulting from the phase difference of the signal within the gate electrode. As a result, a field-effect transistor device capable of amplifying the signal with efficiency can be provided.
On the semiconductor substrate which is a constituent of the field-effect transistor device, since a slot line on the input side for inputting a signal to the field-effect transistor portion is provided, for example, it is possible for the field-effect transistor device to receive the signal from the slot line of the circuit substrate on which that device is mounted via the slot line on the input side. Therefore, it is possible to reduce a signal connection loss at the portion where the field-effect transistor device and the circuit substrate are connected to each other. Furthermore, on the semiconductor substrate of the field-effect transistor device, since a slot line on the output side for outputting a signal of the field-effect transistor portion is provided, for example, it is possible for the field-effect transistor device to output an output signal from the slot line on the output side of that device to the slot line of the circuit substrate on which that device is mounted in a state in which a connection loss is reduced. In the manner described above, as a result of forming a slot line on the input side and a slot line on the output side on the semiconductor substrate of the field-effect transistor device, a signal connection loss is significantly reduced, and thus, the gain of the field-effect transistor device is further increased.
In preferred embodiments of the present invention, for the field-effect transistor device and the circuit substrate, since the slot lines can be bump-connected together so as to allow the conduction of the signal, a variation in impedance at the portion where the field-effect transistor device and the circuit substrate are connected on the signal conduction path can be minimized. As a result, it is possible to suppress the generation of unwanted waves resulting from a variation in impedance.
Furthermore, since the gate-connection-line electrode defines the slot line on the input side and also the slot line on the output side, the field-effect transistor device of preferred embodiments of the present invention can be used in circuits for which gate grounding is required.
Furthermore, in one preferred embodiment of the field-effect transistor device configured in such a manner that the source-connection-line electrode and the drain-connection-line electrode are arranged adjacent to each other with a space provided therebetween, by forming a cut-out portion in at least one of the electrode portion on the drain-connection-line electrode side in the source-connection-line electrode and the electrode portion on the source-connection-line electrode in the drain-connection-line electrode so as to increase the space between the source-connection-line electrode and the drain-connection-line electrode, the isolation between the source-connection-line electrode and the drain-connection-line electrode can be ensured. As a result, it is possible to prevent undesired coupling between the source-connection-line electrode and the drain-connection-line electrode, making it possible to prevent problems resulting from the undesired coupling, that is, problems such as electrical current passing between the source-connection-line electrode and the drain-connection-line electrode and a signal not being supplied to the field-effect transistor portion.
Furthermore, in one preferred embodiment of the field-effect transistor device configured such that the slot line on the input side and the slot line on the output side are arranged along approximately the same straight line with the portion where the field-effect transistor portion is disposed in between, a signal conduction loss can be minimized, and thus, the gain of the field-effect transistor device can easily be further increased.
In one preferred embodiment of the field-effect transistor device that has a plurality of field-effect transistor portions by being configured in such a manner that a plurality of sets of the gate electrodes, the source electrodes, and the drain electrodes are disposed on the same surface of the semiconductor substrate, in manufacturing steps, the plurality of sets of the gate electrode, the source electrode, and the drain electrode can be formed on the surface of the semiconductor substrate at the same time. Therefore, variations in the characteristics of the plurality of the field-effect transistor portions can be almost eliminated. As a result, for example, when a plurality of field-effect transistor portions is to be incorporated into a circuit, the design of the circuit can be made easier.
In addition, in one preferred embodiment of the field-effect transistor device configured in such a manner that, on the semiconductor substrate, an even number of field-effect transistor portions are arranged with a space provided therebetween and that the entire electrode pattern disposed on the surface of the semiconductor substrate is arranged to be line symmetrical with respect to the center line of that entire electrode pattern, which is substantially perpendicular to the direction in which the field-effect transistor portions are arranged, in a case where, for example, a signal output from each field-effect transistor portion of the field-effect transistor device is joined by the slot lines disposed on the circuit substrate, the harmonics of the even mode included in the output signal of each field-effect transistor portion cancel each other and can be eliminated. Due to the fact that the harmonics are one cause of the loss of the fundamental waves, since the harmonics of the even mode can be eliminated in the manner described above, it is possible to reduce the loss of the fundamental waves of the signal, and thus, the gain of the field-effect transistor device can be further increased.
Other features, elements, characteristics and advantages of the present invention will become more apparent from the following detailed description of preferred embodiments with reference to the attached drawings.